The present invention relates to non-volatile memory, e.g., such as NAND Flash memory, and more particularly, this invention relates to the assignment of open logical erase blocks (LEBs) to data streams.
Using Flash memory as an example, the performance characteristics of conventional NAND Flash-based solid state drives (SSDs) are fundamentally different from those of traditional hard disk drives (HDDs). Data in conventional SSDs is typically organized in pages of 4, 8, or 16 kilobyte (KB) sizes. Moreover, page read operations in SSDs are typically one order of magnitude faster than write operations and latency neither depends on the current nor the previous location of operations.
However, in Flash-based SSDs, memory locations are erased in blocks prior to being written to. The size of an erase block unit is typically 256 pages and the erase operations takes approximately one order of magnitude more time than a page program operation. Due to the intrinsic properties of NAND Flash, Flash-based SSDs write data out-of-place whereby a mapping table maps logical addresses of the written data to physical ones. This mapping table is typically referred to as the Logical-to-Physical Table (LPT).
As Flash-based memory cells exhibit read errors and/or failures due to wear or other reasons, additional redundancy may be used within memory pages as well as across memory chips (e.g., RAID-5 and RAID-6 like schemes). The additional redundancy within memory pages may include error correction code (ECC) which, for example, may include Bose-Chaudhuri-Hocquengham (BCH) codes. While the addition of ECC in pages is relatively straightforward, the organization of memory blocks into redundant array of independent disks (RAID)—like stripes is more complex. For instance, individual blocks are retired over time which requires either reorganization of the stripes, or capacity reduction of the stripe. As the organization of stripes together with the LPT defines the placement of data, SSDs typically utilize a Log-Structured Array (LSA) architecture, which combines these two methods.
The LSA architecture relies on out-of-place writes. In this approach, a memory page overwrite will result in writing the memory page data to a new location in memory, marking the old copy of the memory page data as invalid, and then updating the mapping information. Due to the limitations of current NAND memory technology, an invalidated data location cannot be reused until the entire block it belongs to has been erased. Before erasing, though, the block undergoes garbage collection, whereby any valid data in the block is relocated to a new block. Garbage collection of a block is typically deferred for as long as possible to maximize the amount of invalidated data in block, and thus reduce the number of valid pages that are relocated, as relocating data causes additional write operations, and thereby increases write amplification.
A computer-implemented method, according to one embodiment, includes: assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, determining an anticipated throughput of each of the first and second data streams, assigning a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream, and assigning a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream.
A computer program product, according to another embodiment, includes a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a controller to cause the controller to: assign, by the controller, data having a first heat to a first data stream, assign, by the controller, data having a second heat to a second data stream, determine, by the controller, an anticipated throughput of each of the first and second data streams, assign, by the controller, a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream, and assign, by the controller, a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream.
A system according to yet another embodiment, includes: a plurality of non-volatile random access memory blocks configured to store data, and a processor and logic integrated with and/or executable by the processor, the logic being configured to: assign data having a first heat to a first data stream, assign data having a second heat to a second data stream, determine an anticipated throughput of each of the first and second data streams, assign a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream, and assign a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream.
Other aspects and embodiments of the present invention will become apparent from the following detailed description, which, when taken in conjunction with the drawings, illustrate by way of example the principles of the invention.